32Kb cache, 2 way assoc. and 64B line. what is the cache state and line state according to MESI when. Read 0x010F30 then write 0x880F00 then write 0x010F20
Design Verification Engineer Interview Questions
1,114 design verification engineer interview questions shared by candidates
They asked about uvm fundamentals. They were looking for strong uvm experience and asked me to write code for scoreboard, monitor and asked about how to connect them.
difference of Union and Struct (C++). VIPT cache.
There are block box modules, and you know nothing about what they are doing, behaior, output, input. Can you create a verification TB for it?
What's your name , is it [name] ?
Computer Architecture, Coding in SystemVerilog
Design an FSM for a 2-clock system
What is gray code and 8b10b encoding, and why they are useful
Q. What are all run-phases and in detail discussion about it Q. Basic constraints related to dist, and assertion
Cache Coherency, UVM and TLM related, SV concepts, Past projects.
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