first interview 1) setup hold constrains 2) draw VTC of inverter and explain it, how can you move the curve 3) question about the capacitance of inverter 4) given one priority encoder 4:2 implement 16:4 priority encoder 5)implement Mux 4:2 Second interview 1) draw FF using Mux and get the setup, hold and CQ from the FF design 2)Draw SRAM and explain it functionality 3)question about capacitor Jumps
2. Draw Layout of inverter
Explain set up and hold time
Where did you apply [skill listed in resume] in your projects?
Personality questions, achievements and alike
Design an AND gate using a Multiplexer
build a mux2x1 with logic gates build with 2x1mux nand gate
Show me a cross section layout of nand gate using cmos.
Telephonic:Process and Temp variation for delays,Voltage and TEmperature effect on Metal LAyer,Synthesis flow:Inputs.How do u do floorplanning.?Power types and methods to control,DRC,challenges during placementa nd congestion Onsite; First ROund:Whole RTL to Netlist flow in detail,Timing correlation,miller effect,virtual routes),Sceond ROund: How do u solve DC and ICC correlation:DC putting lots of buffers-Reasons,How will u solve clock transition if sizing is not posibble(Explain MErging), 3rd Round : TECH DRC Questions :One problem was given :write a script to replace with right optimized via in power plan .4th Round :STA problems,3 equations -waveforms;derate effects,positive and negative edge flops at capturing end.5th ROund: Custom Bus routing (How to do manually for timing critical path),Script to find occurences of via in design by reference name and reduce runtime by not using get_cells twice.
Questions on digital circuits, VLSI funadmentals, HDL
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