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Interested in learning more about the industry’s most advanced conductor etch technology, Akara®? Hear it straight from one of our experts in a conversation with Counterpoint Research. The conversation covers the challenges of 3D chipmaking, how Akara® overcomes them, and more. Watch now.
Akara: Next Gen of Etching Tech for a New Era of Semiconductors
From learners to leaders, the first cohort of our Microscopy Technician Training Program just graduated! Through this program with Portland Community College, we help students gain hands-on experience with the same equipment used in advanced manufacturing. In just eight weeks, participants learned how to navigate complex imaging tools and apply that knowledge to real-world challenges. It’s all part of building a stronger, more skilled tech workforce in Oregon. Read the blog for more.
A Closer Look at How Lam Research Supports Microscopy Talent Pipeline in Oregon
Not all yield loss is visible on the surface. Mechanical deformation during fabrication can quietly alter device dimensions, until performance takes a hit. We use virtual fabrication with SEMulator3D® to simulate stress, spot hidden risks, and refine process windows before a single wafer is built. Read our blog post to learn more.
Examining Mechanical Deformation in Advanced Logic Devices to Enhance Yield
How do you etch the future into silicon? With DirectDrive®, we introduced a new way to control plasma, built through years of joint research with the National Science Foundation (NSF), UCLA, and the University of Michigan. It’s not just about precision at the atomic level. It’s about rethinking how ideas move from an experiment to high-volume chipmaking. See the power of long-term collaboration via the NSF article.
Now on factory floors: Ultra-precise chip etching technology enabled by NSF-funded plasma science
Breakthroughs in materials science are needed to scale next-generation 3D NAND chips. With its low resistivity and barrierless integration, molybdenum (Mo) brings forth a generational change in semiconductor metallization. Learn more.
Scaling 3D Chips with Molybdenum-Based Metallization
As AI pushes computing boundaries, lowering electrical resistance in 3D chip designs is essential to keep up with data-intensive applications. Learn how our work with molybdenum (Mo) shapes the future of AI.
Breaking Through AI's Invisible Barrier With Molybdenum
Reducing line edge and width roughness in EUV patterns can be tricky, but our latest simulation work with SEMulator3D® shows how ion beam etch (IBE) at an 80° angle makes a real difference. Read the blog post to see the results of our study.
Laser-Focused Results: Improving EUV Line Edge Roughness With Ion Beam Etching
The future of chipmaking doesn’t just rely on innovation at the silicon level — it depends on smarter packaging too. From AI-driven control to precision robotics like our Dextro™ cobot, advanced packaging becomes more adaptive, reliable, and resilient. Get the full overview in Semiconductor Engineering.
Packaging With Fewer People And Better Results
Our latest donation and ongoing collaboration with the University of California, Berkeley, to focus on enabling new fabrication processes for nanoscale semiconductor devices, including Specialty Technologies, needed to support a wide range of real-world applications! Learn more.
Lam Research Donates Leading-Edge Etch System to Accelerate Nanofabrication R&D at UC Berkeley
As transistors shrink into the angstrom era, power integrity and thermal management become critical. Backside power delivery networks (BSPDNs) offer a solution by rerouting power through the wafer’s backside, which reduces congestion and improves efficiency. Learn how BSPDNs influence mechanical stress in gate-all-around (GAA) transistors and what it means for future chip performance.
The Other Side of the Wafer: Transistor Channel Stress in Backside Power Delivery Networks